ARES

Redcode-94 Reference

 # Immediate \$ Direct (Relative) @, * Indirect <, { Predecrement Indirect >, } Postincrement Indirect

Opcode Modifiers

 .A The A-values of both cells adressed are used .B The B-values of both cells adressed are used .AB The A-value of the cell the first operand adresses and the B-value of the cell adressed by the second operand are used .BA The B-value of the cell the first operand adresses and the A-value of the cell adressed by the second operand are used .F Both values of the adressed cells are used, like .A and .B combined .X Both values are used crosswise, like .AB and .BA combined .I The whole instruction is used

Opcodes

 DAT used to store data MOV copies data or whole instructions ADD adds a value to another SUB subtracts a value from another MUL multiplicates two values DIV divides a value by another MOD calculates the remainder of a division JMP defines the next instruction to be stored in the task queue JMZ jump to a cell, if a value is zero JMN jump to a cell, if a value is non-zero DJN decrements a value, and jumps if non-zero CMP compares two values and skips the next instruction, when they were equal SLT compares two values and skips the next instruction, when one is less than the other SPL adds a new entry to the task queue

General Definitions

An instruction consists of an opcode, a modifier, an A-operand, and a B-operand.
An A-operand consists of an A-mode and an A-number.
An A-mode is the addressing mode of an A-operand.
An A-number is an integer between 0 and M-1, inclusive.
A B-operand consists of a B-mode and a B-number.
A B-mode is the addressing mode of a B-operand.
A B-number is an integer between 0 and M-1, inclusive.

Spezific Definitions

The program counter (PC) is the pointer to the location in core of the instruction fetched from core to execute.
The current instruction is the instruction in the instruction register, as copied (prior to execution) from the PC location of core.
The A-pointer points to the instruction the A-operand of the current instruction references in core.
The A-instruction is a copy of the instruction the A-pointer points to in core (as it was during operand evaluation).
The A-value is the A-number and/or the B-number of the A-instruction or the A-instruction itself, whichever are/is selected by the opcode modifier.
The B-pointer points to the instruction the B-operand of the current instruction references in core.
The B-instruction is a copy of the instruction the B-pointer points to in core (as it was during operand evaluation).
The B-value is the A-number and/or the B-number of the B-instruction or the B-instruction itself, whichever are/is selected by the opcode modifier.
The B-target is the A-number and/or the B-number of the instruction pointed to by the B-pointer or the instruction itself, whichever are/is selected by the opcode modifier.

All MARS instructions are executed following the same procedure:

1. The currently executing warrior's current task pointer is extracted from the warrior's task queue and assigned to the program counter.
2. The corresponding instruction is fetched from core and stored in the instruction register as the current instruction.
3. The A-operand of the current instruction is evaluated.
4. The results of A-operand evaluation, the A-pointer and the A-instruction, are stored in the appropriate registers.
5. The B-operand of the current instruction is evaluated.
6. The results of B-operand evaluation, the B-pointer and the B-instruction, are stored in the appropriate registers.
7. Operations appropriate to the opcode.modifier pair in the instruction register are executed. With the exception of DAT instructions, all operations queue an updated task pointer. (How the task pointer is updated and when it is queued depend on instruction execution).
All pointers are PC-relative, indicating the offset from the source of the current instruction to the desired location. All arithmetic is to be done modulo M, with negative values converted in the same manner as during loading as discussed above (P = M + N). Additionally, all reads of core are done modulo the read limit (R) and all writes of core are done modulo the write limit (W). Read offsets O greater than R/2 from the current instruction are converted to backwards offsets of O = O - R. A comparable conversion occurs for write offsets greater than W/2.

Immediate #

An immediate mode operand merely serves as storage for data. An immediate A/B-mode in the current instruction sets the A/B-pointer to zero.

Direct (Relative) \$

A direct mode operand indicates the offset from the program counter. A direct A/B-mode in the current instruction means the A/B-pointer is a copy of the offset, the A/B-number of the current instruction.

Indirect *, @

An indirect mode operand indicates the primary offset (relative to the program counter) to the secondary offset (relative to the location of the instruction in which the secondary offset is contained). An indirect A/B-mode indicates that the A/B-pointer is the sum of the A/B-number of the current instruction (the primary offset) and the B-number of the instruction pointed to by the A/B-number of the current instruction (the secondary offset).

When an asterisk "*" is used as adress mode indicator, then A-value (the A-number of the cell, referenced by the primary offset PC + A-number) is used as secondary offset. The accessed cell is PC + A/B-number + A-value. (ICWS-94 defines adress mode "@" only)

Predecrement Indirect <, {

A predecrement indirect mode operand indicates the primary offset (relative to the program counter) to the secondary offset (relative to the location of the instruction in which the secondary offset is contained) which is decremented prior to use. A predecrement indirect A/B-mode indicates that the A/B-pointer is the sum of the A/B-number of the current instruction (the primary offset) and the decremented B-number of the instruction pointed to by the A/B-number of the current instruction (the secondary offset).

When a opening curly brace "{" is used as adress mode indicator, then A-value (the A-number of the cell, referenced by the primary offset PC + A-number) is used as secondary offset. The accessed cell is PC + (A/B-number - 1) + A-value. (ICWS-94 defines adress mode "<" only)

Postincrement Indirect >, }

A postincrement indirect mode operand indicates the primary offset (relative to the program counter) to the secondary offset (relative to the location of the instruction in which the secondary offset is contained) which is incremented after the results of the operand evaluation are stored. A postincrement indirect A/B-mode indicates that the A/B-pointer is the sum of the A/B-number of the current instruction (the primary offset) and the B-number of the instruction pointed to by the A/B-number of the current instruction (the secondary offset). The B-number of the instruction pointed to by the A/B-number of the current instruction is incremented after the A/B-instruction is stored, but before the B-operand is evaluated (for post-increment A-mode), or the operation is executed (for post-increment indirect B-mode).

When a closing curly brace "}" is used as adress mode indicator, then A-value (the A-number of the cell, referenced by the primary offset PC + A-number) is used as secondary offset. The accessed cell is PC + (A/B-number) + A-value. (ICWS-94 defines adress mode ">" only)

Opcode Modifiers

.A

Instruction execution proceeds with the A-value set to the A-number of the A-instruction and the B-value set to the A-number of the B-instruction. A write to core replaces the A-number of the instruction pointed to by the B-pointer.

For example, a CMP.A instruction would compare the A-number of the A-instruction with the A-number of the B-instruction. A MOV.A instruction would replace the A-number of the instruction pointed to by the B-pointer with the A-number of the A-instruction.

.B

Instruction execution proceeds with the A-value set to the B-number of the A-instruction and the B-value set to the B-number of the B-instruction. A write to core replaces the B-number of the instruction pointed to by the B-pointer.

For example, a CMP.B instruction would compare the B-number of the A-instruction with the B-number of the B-instruction. A MOV.B instruction would replace the B-number of the instruction pointed to by the B-pointer with the B-number of the A-instruction.

.AB

Instruction execution proceeds with the A-value set to the A-number of the A-instruction and the B-value set to the B-number of the B-instruction. A write to core replaces the B-number of the instruction pointed to by the B-pointer.

For example, a CMP.AB instruction would compare the A-number of the A-instruction with the B-number of the B-instruction. A MOV.AB instruction would replace the B-number of the instruction pointed to by the B-pointer with the A-number of the A-instruction.

.BA

Instruction execution proceeds with the A-value set to the B-number of the A-instruction and the B-value set to the A-number of the B-instruction. A write to core replaces the A-number of the instruction pointed to by the B-pointer.

For example, a CMP.BA instruction would compare the B-number of the A-instruction with the A-number of the B-instruction. A MOV.BA instruction would replace the A-number of the instruction pointed to by the B-pointer with the B-number of the A-instruction.

.F

Instruction execution proceeds with the A-value set to both the A-number and B-number of the A-instruction (in that order) and the B-value set to both the A-number and B-number of the B-instruction (also in that order). A write to core replaces both the A-number and the B-number of the instruction pointed to by the B-pointer (in that order).

For example, a CMP.F instruction would compare the A-number of the A-instruction to the A-number of the B-instruction and the B-number of the A-instruction to B-number of the B-instruction. A MOV.F instruction would replace the A-number of the instruction pointed to by the B-pointer with the A-number of the A-instruction and would also replace the B-number of the instruction pointed to by the B-pointer with the B-number of the A-instruction.

.X

Instruction execution proceeds with the A-value set to both the A-number and B-number of the A-instruction (in that order) and the B-value set to both the B-number and A-number of the B-instruction (in that order). A write to to core replaces both the B-number and the A-number of the instruction pointed to by the B-pointer (in that order).

For example, a CMP.X instruction would compare the A-number of the A-instruction to the B-number of the B-instruction and the B-number of the A-instruction to A-number of the B-instruction. A MOV.X instruction would replace the B-number of the instruction pointed to by the B-pointer with the A-number of the A-instruction and would also replace the A-number of the instruction pointed to by the B-pointer with the B-number of the A-instruction.

.I

Instruction execution proceeds with the A-value set to the A-instruction and the B-value set to the B-instruction. A write to core replaces the entire instruction pointed to by the B-pointer.

For example, a CMP.I instruction would compare the A-instruction to the B-instruction. A MOV.I instruction would replace the instruction pointed to by the B-pointer with the A-instruction.

Opcodes

DAT

No additional processing takes place. This effectively removes the current task from the current warrior's task queue.

MOV

MOV replaces the B-target with the A-value and queues the next instruction (PC + 1).

ADD replaces the B-target with the sum of the A-value and the B-value (A-value + B-value) and queues the next instruction (PC + 1). ADD.I functions as ADD.F would.

SUB

SUB replaces the B-target with the difference of the B-value and the A-value (B-value - A-value) and queues the next instruction (PC + 1). SUB.I functions as SUB.F would.

MUL

MUL replaces the B-target with the product of the A-value and the B-value (A-value * B-value) and queues the next instruction (PC + 1). MUL.I functions as MUL.F would.

DIV

DIV replaces the B-target with the integral result of dividing the B-value by the A-value (B-value / A-value) and queues the next instruction (PC + 1). DIV.I functions as DIV.F would. If the A-value is zero, the B-value is unchanged and the current task is removed from the warrior's task queue.

MOD

MOD replaces the B-target with the integral remainder of dividing the B-value by the A-value (B-value % A-value) and queues the next instruction (PC + 1). MOD.I functions as MOD.F would. If the A-value is zero, the B-value is unchanged and the current task is removed from the warrior's task queue.

JMP

JMP queues the sum of the program counter and the A-pointer.

JMZ

JMZ tests the B-value to determine if it is zero. If the B-value is zero, the sum of the program counter and the A-pointer is queued. Otherwise, the next instruction is queued (PC + 1). JMZ.I functions as JMZ.F would, i.e. it jumps if both the A-number and the B-number of the B-instruction are zero.

JMN

JMN tests the B-value to determine if it is zero. If the B-value is not zero, the sum of the program counter and the A-pointer is queued. Otherwise, the next instruction is queued (PC + 1). JMN.I functions as JMN.F would, i.e. it jumps if both the A-number and the B-number of the B-instruction are non-zero. This is not the negation of the condition for JMZ.F.

Attention: pmars handles JMZ.F another way: the jump is done, if A-number or B-number is not zero!

DJN

decrements the B-value and the B-target, then tests the B-value to determine if it is zero. If the decremented B-value is not zero, the sum of the program counter and the A-pointer is queued. Otherwise, the next instruction is queued (PC + 1). DJN.I functions as DJN.F would, i.e. it decrements both both A/B-numbers of the B-value and the B-target, and jumps if both A/B-numbers of the B-value are non-zero.

Attention: pmars handles JMZ.F another way: the jump is done, if A-number or B-number is not zero!

CMP

CMP compares the A-value to the B-value. If the result of the comparison is equal, the instruction after the next instruction (PC + 2) is queued (skipping the next instruction). Otherwise, the the next instruction is queued (PC + 1).

SLT

SLT compares the A-value to the B-value. If the A-value is less than the B-value, the instruction after the next instruction (PC + 2) is queued (skipping the next instruction). Otherwise, the next instruction is queued (PC + 1). SLT.I functions as SLT.F would.

SPL

SPL queues the next instruction (PC + 1) and then queues the sum of the program counter and A-pointer. If the queue is full, only the next instruction is queued.

Tips & Tricks

μCMS α1.6